The complexity of integrated circuits forced designers to use various testing procedures and architectures. One common architecture and protocol is defined at IEEE standard 1149.1 that is also known as JTAG. The IEEE standard 1149.1 defines a test access port (TAP) that may be used to access internal components of an integrated circuit.
JTAG compliant TAPs as well as other debug ports allow unauthorized access to the internal components (such as registers, processors and memories) of integrated circuits.
Various attempts were made for securing integrated circuits. U.S. patent application number 2003/0177373 of Moyer et al., titled “Integrated circuit security and method therefore”, which is incorporated herein by reference, describes an integrated circuit that provides a security key base integrated circuit protection scheme.
U.S. Pat. No. 5,898,776 of Apland et al. titled “security antifuse that prevents readout of some but not other information from a programmed filed programmable gate array”, which is incorporated herein by reference, describes an antifuse that can be programmed to disable access to a JTAG boundary scan register, while allowing. access to a JTAG bypass register.
An integrated circuit can be tested in various occasions and locations. For example, a prototype of the integrated circuit can be tested during a design or research and development stage, it can be field tested during various evaluation stages, within the manufacturer site, within an Original Equipment Manufacturer site, or even at potential customer sites, and the like.
The security level required from an integrated circuit can vary according to the system or application that makes use of that integrated circuit. For example, smart cards can require a higher security level than other applications.
There is a need to provide an efficient security scheme, and especially a security scheme that can be adjusted according to the various development and marketing stages of integrated circuits and a required security level.